1. Field of the Invention
The present invention relates to a signal conversion circuit for converting a parallel signal to a serial signal in which the continuance of identical bits (0s or 1s) is suppressed, which may be used in a video signal transmitter by way of example.
2. Description of the Related Art
In the case of non-return-to-zero (NRZ) encoding and alternate mark inversion (AMI) encoding which are often used as a transmission encoding method, there is the possibility that 0s or 1s continue for a long period of time according to circumstances. This may cause synchronization problems. For this reason, heretofore, various measures have been taken to avoid the continuance of 0s or 1s. For example, an identical-bit-continuance suppression code is used in base band transmission. Systems using the identical-bit-continuance suppression code include various systems such as a system in which NRZ data is converted to a CMI (coded mark inversion) code. Among them there is a system in which (n+1)-bit parallel data is converted to serial data and a complementary code is inserted in one redundant bit for data transmission.
The system includes a parallel input/serial output type of shift register having as many input terminals as there are bits in the parallel data (5 bits in this example). Upon receipt of the parallel data, the shift register is supplied with a load signal LOAD and a shift clock signal CLKS from a timing generator. Thus, the parallel data is loaded into the shift register in synchronization with the load signal LOAD and then serially read from the shift register as serial data SD1 in synchronization with the shift clock signal CLKS. In this case the shift clock signal CLKS is formed such that clock pulses are removed from clock signal CLK1, having a frequency corresponding to six times the transmission rate of the parallel data, one pulse every sixth pulse. Thus, the serial data SD1 read from the shift register will have one redundant bit added to the serial data obtained by serial conversion of the parallel data
That is, the serial data SD1 having a redundant bit is read from the shift register. The data SD1 is entered into a complementary code inserting circuit where, after its sign is inverted, it is subjected to logical processing in synchronization with an insertion timing signal CLOAD so that a complementary code is inserted into the redundant bit. The serial data in which the complementary code has been inserted is output from the inserting circuit in synchronization with the clock signal CLK1.
In this way, serial data SD is obtained by converting 5-bit parallel data to 6-bit data having a complementary code. The transmission of such data SD will suppress the continuance of, for example, 0s in parallel data to a maximum of 5 bits, thus permitting data to be surely reproduced at a repeater or receiver.
However, the signal conversion circuit described above requires a shift register for parallel-to-serial conversion and a complementary code inserting circuit because it is arranged to convert parallel data to serial data having a redundant bit and insert a complementary code in the redundant bit. Moreover, the timing generating circuit is also required to regenerate an insertion timing and a special shift clock signal CLKS as well as a load signal LOAD. Therefore, the conventional signal conversion circuit needs a complex and elaborate circuit arrangement.